The present invention relates to protection of the interconnection structures, known as interconnects, in Ultra-Large Scale Integrated (ULSI) microelectronic circuits including high speed microprocessors, application specific integrated circuits, memory storage devices, and related electronic structures with a multilayered barrier layer. More particularly this invention relates to the structure of cap layers for protecting interconnect-metallization in Back End Of Line (BEOL) structures in such ULSI microelectronic circuits.
In traditional semiconductor devices, aluminum and aluminum alloys have been used as interconnect metallurgies for providing electrical connections to and from devices in BEOL layers of the devices. While aluminum-based metallurgies have been the material of choice for use as metal interconnects in the past, aluminum no longer satisfies requirements as circuit density and speeds for semiconductor devices increase and the scale of devices decreases. Thus, copper is being employed as a replacement for aluminum, because of its lower susceptibility to electromigration failure as compared to aluminum and its lower resistivity.
Despite these advantages, there is the significant problem that copper diffuses readily into the surrounding dielectric material as processing steps continue. To inhibit the copper diffusion, copper interconnects can be isolated by employing protective barrier layers. Such barrier layers include conductive, diffusion barrier liner of tantalum, titanium, or tungsten, in pure or alloy form, along the sidewalls and bottom of the copper interconnection. On the top surface of the copper interconnects caps are provided. Such caps have comprised various dielectric materials, e.g. silicon nitride (Si3N4) “nitride.”
A conventional BEOL interconnect utilizing copper metallization and cap layers described above includes a lower substrate which may contain logic circuit elements such as transistors. An Inter-Level Dielectric (ILD) layer overlies the substrate. The ILD layer may be formed of silicon dioxide (SiO2). However, in advanced interconnects, the ILD layer is preferably a low-k polymeric thermoset material. An adhesion promoter layer may be disposed between the substrate and the ILD layer. A silicon nitride (Si3N4) “nitride” layer is optionally disposed on ILD layer. The nitride layer is commonly known as a hardmask layer or polish stop layer. At least one conductor is embedded in the ILD layer. The conductor is preferably copper in advanced interconnects, but alternatively may be aluminum or other conductive material. When the conductor is copper, a diffusion barrier liner is preferably disposed between the ILD layer and the copper conductor. The diffusion barrier liner is typically comprised of tantalum, titanium, tungsten, or nitrides of these metals.
The top surface of the conductor is made coplanar with the top surface of the hard mask nitride layer, usually by a chemical-mechanical polish (CMP) step. A cap layer, also typically of nitride, is disposed on the conductor and the hard mask nitride layer. The cap layer acts as a diffusion barrier to prevent diffusion of copper from the conductor into the surrounding dielectric material during subsequent processing steps. High Density Plasma (HDP) Chemical Vapor Deposition (CVD) films such as nitride provide superior electromigration protection, as compared to Plasma Enhanced (PE) CVD films, because HDP CVD films more readily stop the movement of copper atoms along the interconnect surface in the cap layer.
However there is the problem that in a conventional HDP deposition process, a seam is formed in the HDP CVD cap layer, and a crack in the cap layer often develops at this seam due to stress within the structure. If the crack develops in a portion of the cap layer overlying a copper conductor, the copper conductor may be readily exposed to moisture and other sources of oxygen. If the crack develops in a portion of the cap layer overlying the ILD, the copper conductor may be exposed to moisture diffusing through the ILD. In the latter case, the seam is of relatively minor concern in interconnects utilizing silicon dioxide as the ILD material, because the rate of moisture diffusion through silicon dioxide is very low. However, in interconnects utilizing a low-k polymeric thermoset dielectric material, this seam is of greater concern, because the rate of diffusion of moisture through most spin-on and CVD low-k materials is relatively high. Moreover, any crack in the cap layer may lead to copper diffusion into the ILD through the seam leading to formation of a copper nodule under the cap layer. Such a copper nodule may lead to short circuits due to leakage of current between adjacent interconnect lines.
Another significant disadvantage occurs when HDP CVD films are integrated with low-k dielectric materials. The energetic reactions of an HDP CVD process can enable interaction with and within the low-k materials causing undesirable changes to occur. Such changes in low-k dielectric materials can be significantly mitigated by the use of PE CVD films. Moreover, in typical PE CVD films, no seam is formed during the deposition process. For this reason, PE CVD cap layers have been used to cap copper interconnects in earlier ground-rule devices. In more advanced ground-rule devices, PE CVD films have been found to be inferior to cap layers formed by other deposition techniques such as HDP CVD because of poor adhesion to the copper surface. PE CVD films may delaminate and form blisters over patterned copper lines, particularly during subsequent dielectric depositions, metallization, and chemical-mechanical polishing.
After being deposited onto copper metallurgy, additional insulating layers generally will be deposited over the cap layer. However, subsequent deposition of insulating layers onto the cap layer will produce stress which can cause the cap layer to peel from the copper surface. This delamination results in several catastrophic failure mechanisms, including lifting interlayer dielectrics, lifting copper conductors, copper diffusion from uncapped copper lines, and electromigration. Such results are generally seen in dual damascene processing where delamination of the silicon nitride hardmask layer generally occurs during copper chemical-mechanical polishing.
Commonly assigned U.S. Pat. No. 6,887,783 Chen et al. entitled “Bilayer HDP CVD/PE CVD Cap in Advanced BEOL Interconnect Structures and Method Thereof” describes a Back-End-Of-Line (BEOL) metallization structure including a bilayer diffusion barrier or cap, with a first cap layer formed of a dielectric material preferably deposited by a high density plasma chemical vapor deposition (HDP CVD) process, and with a second cap layer formed of a dielectric material preferably deposited by a plasma-enhanced chemical vapor deposition (PE CVD) process. The bilayer diffusion barrier or cap is adapted for use with interconnects comprising low-k dielectric material for the inter-layer dielectric (ILD) and copper for the conductors.
Commonly assigned U.S. Pat. No. 7,081,673 Hedrick et al. “Multilayered Cap Barrier in Microelectronic Interconnect Structures” describes a low-k multilayered dielectric diffusion barrier having at least one low-k sublayer and at least one air barrier sublayer. The multilayered dielectric diffusion barrier layer provides a metal diffusion barrier as well as an air permeation barrier. The low-k multilayered dielectric diffusion barrier layer is provided to gain in chip performance through a reduction in capacitance between conducting metal features and an increase in reliability, because the multilayered dielectric diffusion barrier layer is impermeable to air and prevents metal diffusion.
FIG. 1 shows a prior art example from Hedrick et al. of an interconnect 40A, with multiple levels 1000, with each level 1000 including both a via level 1100 and a line level 1200. The interconnect 40A contains conducting metal features 33 that traverse through the structure and may have interfaces with a diffusion barrier liner 34 composed of metal. The conducting metal features 33 and diffusion barrier liner 34 are surrounded by dielectric layers. The dielectric layers in the via level include a low dielectric constant layer 32 and a multilayered-dielectric-diffusion-capping-barrier layer 39 that is comprised of at least two sublayers, an air barrier sublayer 36 and a low-k sublayer 38. In the line level 1200, the dielectric layers include a low dielectric constant layer 31 and an optional hardmask dielectric 41. Optionally, a dielectric etch stop layer 37 may be placed between the low dielectric constant layers in via level dielectric layer 32 and line level dielectric layer 31. The low dielectric constant material in the via level dielectric layer 32 and line level dielectric layer 31 may be identical or may differ in chemical composition.
FIG. 2 shows another a prior art example from Hedrick et al. of an interconnect 40B with multiple levels 1000, with each level 1000 including both a via level 1100 and line level 1200. The interconnect 40 of FIG. 2 contains conducting metal features 33 that traverse through the structure and may have interfaces with a diffusion barrier liner 34. The conducting metal features 33 and diffusion barrier liner 34 are surrounded by dielectric layers. The dielectric layers in the via level include the inventive multilayered-dielectric-diffusion-capping-barrier layer 39 that comprised of at least two sublayers including air barrier sublayer 36 and low-k sublayer 38. The dielectric layers in the line level include a low dielectric constant layer 31 and optional hardmask dielectric layer 41. Optionally, a dielectric etch stop layer 37 may be placed between low dielectric constant layers 31 and multilayered-dielectric-diffusion-capping-barrier layer 39.
FIG. 3 shows yet another prior art example from Hedrick et al. of an interconnect 40C, with multiple levels 1000, with each level 1000 including both a via level 1100 and line level 1200. The interconnect 40C contains conducting metal features 33 that traverse through the structure and may have interfaces with a diffusion barrier liner 34. The conducting metal features 33 and diffusion barrier liner 34 are surrounded by several dielectric layers. The dielectric layers in the line level include a low dielectric constant material 43. The dielectric layers in the via level include the identical low dielectric constant material 43 in regions not directly underlying conducting metal lines, a chemically different low dielectric constant material 42 which is present under conducting metal lines 33, and a multilayered-dielectric-diffusion-capping-barrier layer 39. Optionally, a dielectric etch stop layer 37 may be placed between the low dielectric constant material 42 and the diffusion barrier liner 34 thereabove.
US patent Application 2006/0113672 of Wang et al. entitled “Improved HDP-Based ILD Capping Layer” teaches that the upper surface of any Cu conductor (typically a wire, as vias are in contact with a bottom surface of an overlying conductor) must be protected from harm by processes such as oxidation. Wang et al. states that “to cap the upper surface of the copper interconnection, a ‘capping layer’ of a dielectric material such as silicon nitride (Si3N4) is typically employed. The capping layer is also referred to as a ‘passivation layer’. Often the passivation layer must also function as an etch stop layer during subsequent processing, however materials which perform best as etch stop layers often do not perform best as passivation layers. For example, silicon oxynitride, SiON, is useful as an etch stop layer but it is less desirable as a passivation layer because of delamination which can occur between copper and silicon oxynitride. Silicon nitride, ‘SiN’, avoids the delamination problem, and is a preferred passivation material, but is less desirable as an etch stop layer.” Wang et al also states as follows: “A cap nitride stack which prevents etch penetration to the HDP nitride while maintaining the electromigration benefits of HDP nitride atop Cu. In one embodiment, the stack comprises a first layer of HDP nitride and a second layer of a Si—C—H compound disposed over the first layer. The Si—C—H compound is for example BLoK, or N-BLoK (Si—C—H—N), and is selected from a group of materials that has high selectivity during via RIE such that RIE chemistry from the next wiring level does not punch through. Carbon and nitrogen are the key elements. In another embodiment, the stack comprises a first layer of an HDP nitride, followed by a second layer of UVN (a plasma nitride), and a third layer comprising HDP nitride disposed over the second layer.”
Wang et al describes a problem with a bilayer of a UVN/HDP nitride capping layer formed by an UVN film and an HDP nitride film, which is that in forming a via hole, the Reactive Ion Etching (RIE) process continues too deep and punches through the UVN film and lands on the HDP film. If the UVN is completely missing under a via hole, the via RIE will reach down to the HDP nitride film, which results in problems. A seam in the HDP nitride can become an ingress path for copper (Cu) to react with moisture, which leads to volume expansion and rupture of the capping layer. Also, there is a possible reaction during via RIE through the seam.
Wang et al. suggest that the problem of poor selectivity between UVN and silicon dioxide (SiO2) can be solved by using N-BLoK (or BLoK) instead of UVN in the capping layer, over the HDP nitride layer. BLoK is a Si—C—H compound made by Applied Materials Tool. N-BLoK is the Si—C—H—N compound made by Applied Materials Tool. Since N-BLoK is mostly Si—C—H—N, the selectivity between SiO2 and N-BLoK (or BLoK) is large and the via RIE process would stop on the N-BLoK (or BLoK) without risking damage to the HDP capping layer. BLoK and N-BLoK are referred to as silicon carbide and silicon carbonitrides (nitrogen doped silicon carbide), respectively.
Wang et al teaches that it is important to have HDP nitride as the lower layer on the embedded copper conductor to provide a good interface between Cu and the nitride capping layer. Therefore HDP nitride is the preferred material to be used for the lower layer in a multi-layer capping layer. A subsequent layer(s) can be N-BLoK over the HDP first layer, or HDP over UVN over the HDP first layer, or HDP over N-BLoK over the HDP layer, to solve the selectivity issue during the via oxide RIE.
FIG. 4A depicts a Wang et al. prior art interconnect 500, elevational, cross-section, containing two wiring levels 510 and 530. A copper conductor 520 is shown embedded in a trench in a first ILD layer 512. A barrier layer 518 is provided under and on the side wall of the copper conductor 520. The top surface of the copper conductor 520 is essentially coplanar with the surface of the ILD 512, typically as a result of Chemical Mechanical Polishing (CMP). A capping layer 522 is deposited over the device 500 covering the top surface of the ILD 512 and the top surface of the copper conductor 520. A second ILD layer 532 is formed over the capping layer 522, and a via hole 536 (is formed in the second ILD layer 532. In FIG. 4B, the ILD layers 512 and 532 may both be silicon dioxide (SiO2.) However, a suitable low-k material was described as being acceptable. In the interconnect 500, the second capping layer 526) of the overall capping layer 522 comprises N-BLoK (or BLoK.)
FIG. 4B depicts another Wang et al. prior art interconnect 600, elevational, cross-section, containing two wiring levels 610 and 630. A copper conductor 620 is shown which is embedded in a trench in a first ILD layer 612. A barrier layer 618 is provided under and on the side wall of the copper conductor 620. The top surface of the copper conductor 620 is essentially coplanar with the surface of the ILD 512, typically as a result of Chemical Mechanical Polishing (CMP). A capping layer 622 is deposited over the device 600 covering the top surface of the ILD 612 and the top surface of the copper conductor 620. A second ILD layer 632 is formed over the capping layer 622, and a via hole 636 is formed in the second ILD layer 632. of the ILD 612 and the copper conductor 620. The interconnect structure 600 of FIG. 4B is different from the interconnect structure 500 of FIG. 4A in that the multi-layer capping layer 622 comprises three layers, rather than two layers. More particularly, a layer 626 of UVN 626 (a plasma nitride) is deposited over an initial layer 624 of HDP nitride (HDP-1). Then, a second layer 628 of HDP nitride (HDP-2) is deposited over the layer 626 of UVN. The first layer 624 of HDP nitride (HDP-1) is on the surface of the ILD 612 and the copper conductor 620.
U.S. patent Application 2006/0024955 of Frohberg et al. entitled “Nitrogen-Free ARC/Capping Layer and Method of Manufacturing the Same” describes a “nitrogen-free ARC/capping layer in a low-k layer stack, which, in particular embodiments, is comprised of carbon-containing silicon dioxide, wherein the optical characteristics are tuned to conform to the 193 nm lithography. Moreover, the ARC/capping layer is directly formed on the low-k material, thereby also preserving the integrity thereof during an etch and chemical mechanical polishing process.” The Frohberg et al. application 2006/0024955 provides for capping dielectric (as a hard mask), but it is not related to capping which provides a Cu barrier layer.
U.S. patent Application 2006/0046495 of Frohberg et al. entitled “Technique for Enhancing the Fill Capabilities in an Electrochemical Deposition Process by Edge Rounding of Trenches” describes that “During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabilities of subsequent metal deposition processes. In one particular embodiment, an additional etch process is performed after etching through the capping layer and the low-k dielectric layer and after resist removal.” The Frohberg et al. application 2006/0046495 also provides for capping dielectric (as a hard mask), and it also is not related to capping which provides a Cu barrier layer.
The utilization of materials that serve as metal diffusion barriers in metal interconnects, that are part of Ultra-Large Scale Integrated (ULSI) circuits and microelectronic devices, is typically required to generate reliable devices since low-k InterLayer Dielectrics (ILDs) do not prevent metal diffusion. The placement of such metal diffusion barrier materials in an interconnect can differ and the quality of the film will depend on the deposition and processing methods.
Commonly assigned U.S. Pat. No. 6,911,400 of Colburn et al. entitled “Nonlithographic Method to Produce Self-Aligned Mask, Articles Produced by Same and Compositions for Same” shows an interconnect with an InterLayer Dielectric (ILD), metal wiring, a liner barrier layer, and cap barrier layer. The interconnect has multiple levels comprised of multiple wiring levels, a via layer and a line level. Colburn et al. indicates that materials for the ILD have low dielectric constants (k<3) including carbon-doped silicon dioxide (silicon oxycarbide or SiCOH dielectrics); fluorine-doped silicon oxide (FluoroSilicate Glass (FSG)); spin-on glasses; SilSesQuioxanes (SSQs), including Hydrogen SSQ (HSSQ), Methyl SSQ (MSSQ) and mixtures or copolymers of HSSQ and MSSQ; and any silicon-containing low-k dielectric. The ILD may contain pores to further reduce the dielectric constant, and other dielectrics may be used. Alternatively the structure which includes the metal wiring, liner barrier layer, and cap barrier layer is modified to include multiple ILD layers with dielectric hardmask layers therebetween. The materials for the ILD have low dielectric constants (k<3), e.g. an organic polymer thermoset, and may be selected from the group SiLK™, (a product of Dow Chemical Co.), Flare™ (a product of Honeywell), and other polyarylene ethers, or other organic polymer thermoset dielectrics. Materials for the dielectric hardmask include silicon carbides, carbon-doped silicon dioxide (silicon oxycarbide or SiCOH dielectrics); fluorine-doped silicon oxide (FSG); spin-on glasses; and SSQs.
Diffusion barrier layers comprised of dielectrics including, for example, silicon nitrides, silicon carbides, and silicon carbonitrides, are commonly used in microelectronic devices. These materials are normally deposited by Chemical Vapor Deposition (CVD) and PE CVD methods and can be deposited as continuous films. Unlike metal barrier layers, dielectric layers can be deposited as blanket films and can be placed between conducting metal lines.
In various prior art structures, thin wires, (and optionally fat wires) are formed in a low dielectric constant (k) material having a dielectric constant between about 3 and about 3.5. In other prior art structures, thin wires (and optionally the fat wires) are formed in an Ultra Low K (ULK) material, where K is the dielectric constant, having a dielectric constant less than 3 and potentially as low as 1.8. Typically, the ULK materials have dielectric constants within a range from 1.8 to 3.
Use of ultraviolet (UV) light to modify the bulk of a SiCOH dielectric film is well known. As is known in the art, UV radiation may be used to penetrate into a dielectric of the SiCOH composition to strengthen the bulk of the dielectric to raise the elastic modulus. For example, U.S. Pat. No. 6,566,278 to Harvey teaches the use of UV light to make the bulk of a SiCOH film denser. Specifically, the '278 patent teaches the conversion of Si—OH groups in the bulk of the film into Si—O—Si linkages. The resulting film disclosed in the '278 patent has “bonds characteristic of an ordered silicon oxide lattice” after UV irradiation. To accomplish this, the UV radiation breaks Si—O and O—H bonds and causes formation of more Si(O)3 and Si(O)4 structures (with 3 or 4 bonds to Si, respectively) and these render the material stronger and with a higher elastic modulus.
However, while UV cure has been proven to be beneficial for ultra low-k ILD/IMD (Inter Metal Dielectric) integration, UV cure also increases/changes the stress of the underlying cap layer (i.e., N-Blok/Nitride) such that it changes from a compressive to a highly tensile film. The observed change in stress increases the dielectric (k) value of the cap layer and adversely impacts the mechanical integrity of the structure.
A known solution to the effect of UV cure is to compensate for the change in stress by starting with a highly compressive N-Blok film. Consequently, this change will likely increase the dielectric constant, k, and impact its Cu oxidation/diffusion properties. The dielectric (k) value of the cap layer must be reduced for high performance sub-50 nm nano-CMOS devices. Bilayer caps with an embedded nano-Blocking UV film will minimize the stress change, while maintaining a reduced total capacitance of the structure.